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fujitsu semiconductor data sheet copyright?2011 fujitsu semiconductor limited all rights reserved 2011.6 memory fram 16 k (2 k 8) bit i 2 c MB85RC16 description the MB85RC16 is an fram (ferroelectric random access memory) chip in a configuration of 2,048 words 8 bits, using the ferroelectric process and silicon gate cmos process technologies for forming the nonvolatile memory cells. unlike sram, the MB85RC16 is able to retain data without using a data backup battery. the memory cells used in the MB85RC16 have at least 10 10 read/write operation endurance per bit, which is a significant improvement over the number of read and write operati ons supported by other nonvolatile memory products. the MB85RC16 can provide writing in one byte units because the long wr iting time is not required unlike flash memory and e 2 prom. therefore, the writing completion waiting sequence like a write busy state is not required. features ? bit configuration : 2,048 words 8 bits ? operating power supply voltage : 2.7 v to 3.6 v ? operating frequency : 1 mhz (max) ? two-wire serial interface : fully controllable by tw o ports: serial clock (scl) and serial data (sda). ? operating temperature range : ? 40 c to + 85 c ? data retention : 10 years ( + 75 c) ? read/write endurance : 10 10 times ? package : plastic / sop, 8-pin (fpt-8p-m02) ? low power consumption : operating current 0.1ma (max: @1 mhz), standby current 0.1 a (typ) ds501-00001-2v0-e www..net
MB85RC16 2 ds501-00001-2v0-e pin assignment pin functional descriptions pin number pin name functional description 1 to 3 nc unconnected pins leave it unconnected. 4 vss ground pin 5sda serial data i/o pin this is an i/o pin of serial data for perf orming bidirectional communication of mem- ory address and writing or reading data. it is possible to connect some devices. it is an open drain output, so a pull-up resistance is re quired to be connected to the external circuit. 6scl serial clock pin this is a clock input pin for input/output ti ming serial data. data is sampled on the rising edge of the clock and output on the falling edge. 7wp write protect pin when write protect pin is ?h? level, writ ing operation is disabled. when write pro- tect pin is ?l? level, the entire memory region can be overwritten. reading operation is always enabled regardless of the write protect pin state. the write protect pin is internally pulled down to vss pin, and that is recognized as ?l? level (the state that writing is enabled) when t he pin is the open state. 8 vdd supply voltage pin v ss sda n c v dd scl n c n c w p 8 7 6 5 4 3 2 1 (top view) (fpt-8p-m02)
MB85RC16 ds501-00001-2v0-e 3 block diagram i 2 c (inter-integrated circuit) the MB85RC16 has the two-wire serial interface and the i 2 c bus, and operates as a slave device. the i 2 c bus defines communication roles of ?master? and ?s lave? devices, with the master side holding the authority to initiate control. furthermore, a i 2 c bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. ? i 2 c interface system configuration example w p sda scl row decoder memory address counter fram array 2,048 8 serial/parallel converter column decoder/sense amp/ write amp control circuit scl v dd sda i 2 c bus master i 2 c bus MB85RC16 i 2 c bus other slave pull-up resistors
MB85RC16 4 ds501-00001-2v0-e i 2 c communication protocol the i 2 c bus provides communication by two wires only, therefore, the sda input should change while scl is the ?l? level. however, when starting and stopping the communication sequence, sda is allowed to change while scl is the ?h? level. ? start condition to start read or write operations by the i 2 c bus, change the sda input from the ?h? level to the ?l? level while the scl input is in the ?h? level. ? stop condition to stop the i 2 c bus communication, change the sda input from the ?l? level to the ?h? level while the scl input is in the ?h? level. in the reading operation, in putting the stop condition finishes reading and enters the standby state. in the writing operation, inputting the stop condition finishes inputting the rewrite data. ? start condition, stop condition note : the fram device does not need the programming wait time (t wc ) after issuing the stop condition during the write operation. scl sda start stop
MB85RC16 ds501-00001-2v0-e 5 acknowledge (ack) in the i 2 c bus, serial data including memory address or me mory information is sent in units of 8 bits. the acknowledge signal indicates that every 8 bits of the data is successfully sent and received. the receiver side usually outputs the ?l? level every time on the 9th scl clock after every 8 bits are successfully trans- mitted. on the transmitter side, the bus is temporarily released on this 9th cl ock to allow the acknowledge signal to be received and checked. du ring this released period, the receiver side pulls the sda line down to indicate that the communication works correctly. if the receiver side receives the stop condition be fore transmitting the acknow ledge ?l? level, the read operation ends and the i 2 c bus enters the standby state. if the ac knowledge ?l? level is not detected, and the stop condition is not sent, the bus remains in the released state without doing anything. ? acknowledge timing overview diagram memory address structure the MB85RC16 has the memory addr ess buffer to store the 11-bit information for the memory address. as for byte write, page write and random read commands, the complete 11- bit memory address is configured by inputting the memory upper address (3 bits) and the memory lower address (8 bits), and saving to the memory address buffer and access to the memory is performed. as for a current address read comman d, the complete 11-bit memory addre ss is configured by inputting the memory upper address (3 bits) and by the memory ad dress lower 8-bit which has saved in the memory address buffer, and saving to the memory address bu ffer and access to the memory is performed. scl 123 8 9 sda start ack the transmitter side should always release sda on the 9th bit. at this time, the receiver si de outputs a pull-down if the receive of the previous 8 bit works correctly (ack response).
MB85RC16 6 ds501-00001-2v0-e device address word following the start condition, the 8 bit device address wo rd is input. inputting the device address word decides whether the master or the slave drives the data line. however, the clock is always driven by the master. the device address word (8bits) consists of a device ty pe code (4bits), memory upper address code (3bits), and a read/write code (1bit). ? device type code (4bits) the upper 4 bits of the device address word are a device type code that identifies the device type, and are fixed at ?1010? for the MB85RC16. ? memory upper address code (3bits) following the device type code, the 3 bits of the memory upper address code are input. the slave address selection is not performed by the external pin setting on this device. these 3 bits are not the setting bits for the slave address, but the upper 3-bit setting bits for the memory address. ? read/write code (1bit) the 8th bit of the device address word is the r/w (r ead/write) code. when the r/w code is ?0? input, a write operation is enabled, and the r/w code is ?1? input, a read operation is enabled for the MB85RC16. if the device code is not ?1010?, the r ead/write operation is not performe d and the standby state is chosen.
MB85RC16 ds501-00001-2v0-e 7 data structure the master inputs the device address word (8 bits) following the start condition, and then the slave outputs the acknowledge ?l? level on the ninth bit. after conf irming the acknowledge response, the sequential 8-bit memory lower address is input, to the byte write, page write and random read commands. as for the current address read command, inputting the memory lower address is not performed, and the address buffer lower 8-bit is used as the memory lower address. when inputting the memory lower address finishes, the slave outputs the acknowledge ?l? level on the ninth bit again. afterwards, the input and the output data continue in 8-bi t units, and then the acknowledge ?l? level is output for every 8-bit data. ? device address word .. .. start ack (sda is the "l" le v el) 1234567 8 91 2 scl sda ack start condition read/ w rite code memory upper address de v ice code a s s 10 10 a2 a1 a0 r/ w a access from master access from slave
MB85RC16 8 ds501-00001-2v0-e fram acknowledge -- polling not required the MB85RC16 performs the high speed write operations, so any waiting time for an ack* by the acknowl- edge polling does not occur. *: in e 2 prom, the acknowledge polling is performed as a prog ress check whether rewriting is executed or not. it is normal to judge by the 9th bit of acknowledge w hether rewriting is performed or not after inputting the start condition and then the device addr ess word (8 bits) during rewriting. write protect (wp) the entire memory array can be write protected by sett ing the wp pin to the ?h? level. when the wp pin is set to the ?l? level, the entire memory array will be rewr itten. reading is allowed regardless of the wp pin's ?h? level or ?l? level. do not change the wp signal level during the commun ication period from the st art condition to the stop condition. note : the wp pin is pulled down internally to vss pin, t herefore if the wp pin is open, the pin status is detected as the ?l? level (write enabled).
MB85RC16 ds501-00001-2v0-e 9 command ? byte write if the device address word (r/w ?0? input) is sent after the start condition, an ack responds from the slave. after this ack, write memory addresses and write data are sent in the same way, and the write ends by generating a stop condition at the end. ? page write if data is continuously sent after the following ad dress when the same comm and (expect stop condition) as byte write was sent, a page write is performed. the memory address rolls over to first memory address (000 h ) at the end of the address. therefore, if more than 2 kbytes are sent, the data is overwritten in order starting from the start of the memory address that was written first. start condition stop condition ack (sda is the "l" le v el) a s p lsb msb xxx xxxxxxxx s a2 a1 a0 a a a p address lo w 8b its w rite data 8b its 0 1 010 access from master access from slave start condition stop condition ack (sda is the "l" le v el) a s p s a2 a1 a0 a a a a p address lo w 8b its w rite data 8b its w rite data ... 0 1 010 access from master access from slave
MB85RC16 10 ds501-00001-2v0-e ? current address read if the last write or read operation finishes correctly up to the end of stop conditio n, the memory address that was accessed last remains in the memory address buffer (the length is 11 bits). when sending this command without turning the power off, it is possible to read from the memory address n+1 which adds 1 to the total 11-bit memory address n, which consists of the memory upper address 3-bit from the device address word input and the lower 8-bit of the memory address buffer. if the memory address n is the last address, it is possible to read with rolling over to the head of the memory address (000 h ). the current address (address that the memory address buff er indicates) is undefined immediately after turning the power on. ? random read the one byte of data from the memory address as saved in the memory address buffer can be read out synchronously to scl by specifying the address in the same way as for a write, and then issuing another start condition and sending the device address word (r/w ?1? input). setting values for the first a nd the second memory upper addr ess codes should be the same. the final nack (sda is the ?h? level) is issued by the re ceiver that receives the data. in this case, this bit is issued by the master side. start condition stop condition ack (sda is the "l"le v el) a s p n ack (sda is the "h" le v el) n s a2 a1 a0 a n p read data 8b its (n+1) memory address 1 1 010 access from master access from slave start condition stop condition ack (sda is the "l" le v el) 001 b 01101111 b 001 b a s p n ack (sda is the "h" le v el) n n address s a2 a1 a0 a a p address lo w 8b its 0 1 010 s a2 a1 a0 a 1 1010 read data 8b its n access from master access from slave (input example) when reading memory address 16f h :
MB85RC16 ds501-00001-2v0-e 11 ? sequential read data can be received continuously following the devi ce address word (r/w ?1? input) after specifying the address in the same way as for random read. if th e read reaches the end of address for the MB85RC16, the read address automatically rolls over to first memory address (000 h ). stop condition ack (sda is the "l" le v el) a p n ack (sda is the "h" le v el) n aa a n p read data 8b its read data 8b its read data ... ... access from master access from slave
MB85RC16 12 ds501-00001-2v0-e absolute maximum ratings *: these parameters are based on the condition that vss is 0 v. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. recommended operating conditions *: these parameters are based on the condition that vss is 0 v. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application out side the listed conditions are advised to contact their representatives beforehand. parameter symbol rating unit min max power supply voltage* v dd ? 0.5 + 4.0 v input voltage* v in ? 0.5 v dd + 0.5 ( 4.0) v output voltage* v out ? 0.5 v dd + 0.5 ( 4.0) v ambient temperature t a ? 40 + 85 c storage temperature tstg ? 40 + 125 c parameter symbol value unit min typ max power supply voltage* v dd 2.7 3.3 3.6 v ?h? level input voltage* v ih v dd 0.8 ? v dd + 0.5 ( 4.0) v ?l? level input voltage* v il ? 0.5 ? + 0.6 v ambient temperature t a ? 40 ? + 85 c
MB85RC16 ds501-00001-2v0-e 13 electrical characteristics 1. dc characteristics (within recommended operating conditions) *1: applicable pin: scl,sda *2: applicable pin: sda parameter symbol condition value unit min typ max input leakage current* 1 |i li |v in = 0 v to v dd ?? 1 a output leakage current* 2 |i lo |v out = 0 v to v dd ?? 1 a operating power supply current i cc scl = 1 mhz - ? 70 100 a standby current i sb scl, sda = v dd wp = 0v or v dd or open t a = + 25 c ? 0.1 1 a ?l? level output voltage v ol i ol = 2 ma ?? 0.4 v input resistance for wp pin r in v in = v il (max) 50 ?? k v in = v ih (min) 1 ?? m
MB85RC16 14 ds501-00001-2v0-e 2. ac characteristics (within recommended operating conditions) ac characteristics were measured under the following measurement conditions. power supply voltage : 2.7 v to 3.6 v operating temperature : ? 40 c to + 85 c input voltage amplit ude : 0.3 v to 2.7 v input rise time : 5 ns input fall time : 5 ns input judge level : v dd /2 output judge level : v dd /2 parameter symbol value unit standard mode fast mode min max min max scl clock frequency fscl 0 400 0 1000 khz clock high time t high 600 ? 400 ? ns clock low time t low 1300 ? 600 ? ns scl/sda rise time t r ? 300 ? 300 ns scl/sda fall time t f ? 300 ? 100 ns start condition hold t hd:sta 600 ? 250 ? ns start condition setup t su:sta 600 ? 250 ? ns sda input hold t hd:dat 0 ? 0 ? ns sda input setup t su:dat 100 ? 100 ? ns sda output hold t dh:dat 0 ? 0 ? ns stop condition setup t su:sto 600 ? 250 ? ns sda output access after scl fall t aa ? 900 ? 550 ns pre-charge time t buf 1300 ? 500 ? ns noise suppression time constant on scl, sda t sp ? 50 ? 50 ns
MB85RC16 ds501-00001-2v0-e 15 3. ac timing definitions 4. pin capacitance 5. ac test load circuit parameter symbol conditions value unit min typ max i/o capacitance c i/o v dd = v in = v out = 0v, f = 1 mhz, t a = + 25 c ?? 15 pf input capacitance c in ?? 15 pf start start stop stop v alid scl sda scl sda scl sda v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v ih v ih t su:dat t su:sta t hd:sta t high t lo w t dh:dat 1/fscl t su:sto t hd:dat v ih v ih v ih v il v il v il v il v il v il v il v il t bu f t f t r t f t r t aa t sp 3.3 v 100 pf o u tp u t
MB85RC16 16 ds501-00001-2v0-e power on sequence notes on use ? data written before performing ir reflow is not guaranteed after ir reflow. ?v dd is required to be rising from 0 v because turning the power on from an intermediate level may cause malfunctions, when the power is turned on. parameter symbol value unit min max sda, scl level hold time during power down tpd 85 ? ns sda, scl level hold time during power up tpu 85 ? ns power supply rise time tr 0.01 50 ms power supply fall time tf 0.01 50 ms power off time toff 50 ? ms 0 v sda, scl > v dd 0. 8 * sda, scl > v dd 0. 8 * tpd tp u tr tf v il (max) 1.0 v v ih (min) 2.7 v v dd sda, scl : don ' t care sda, scl sda, scl 0 v v il (max) 1.0 v v ih (min) 2.7 v v dd toff * : sda, scl (max) < v dd + 0.5 v
MB85RC16 ds501-00001-2v0-e 17 ordering information part number package remarks MB85RC16pnf-g-jne1 8-pin, plastic sop (fpt-8p-m02) MB85RC16pnf-g-jnere1 8-pin, plastic sop (fpt-8p-m02) embossed carrier tape
MB85RC16 18 ds501-00001-2v0-e package dimension please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 8-pin plastic sop lead pitch 1.27 mm package width package length 3.9 mm 5.05 mm lead shape gullwing sealing method plastic mold mounting height 1.75 mm max weight 0.06 g 8-pin plastic sop (fpt-8p-m02) (fpt-8p-m02) c 2002-2010 fujitsu semiconductor limited f08004s-c-4-9 1.27(.050) 3.900.30 6.000.40 .199 ?.008 +.010 ?0.20 +0.25 5.05 0.13(.005) m (.154.012) (.236.016) 0.10(.004) 14 5 8 0.440.08 (.017.003) ?0.07 +0.03 0.22 .009 +.001 ?.003 45 0.40(.016) "a" 0~8 0.25(.010) (mounting height) details of "a" part 1.550.20 (.061.008) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.150.10 (.006.004) (stand off) 0.10(.004) * 1 * 2 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * 1 : these dimensions include resin protrusion. note 2) * 2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder.
MB85RC16 ds501-00001-2v0-e 19 memo
MB85RC16 fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 902 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersi ble repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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